1. https://www.springer.com/gp/book/9781461494041
2. https://www.crcpress.com/Design-of-Low-Power-Coarse-Grained-Reconfigurable-Architectures/Kim-Mahapatra/p/book/9781138113527
3. https://www.amazon.com/Data-Integrity-Chip-Interconnects-Communication/dp/3639203666
Book Chapters
1. Kim* and Mahapatra, “Design of Low-Power Coarse-Grained Reconfigurable Architectures”. CRC Press. 2010
2. A. Biswas*, S., Mohan* and R. Mahapatra, “Semantic Technologies for Searching in e-Science Grids”, in Semantic e-Science, H. Chen, Y. Wang and K. Cheung, Eds., in Springer Annals of Information Systems AoIS. (2010)
3. M. Nolan* and R. Mahapatra, “A TDM Test Scheduling Method for Network on Chip,” Microprocessor Test and Verification, IEEE Computer Society Press, 2006.
4. Rabi N. Mahapatra, Guest Editor, Special Issue on Embedded System Codesign, International Journal on Microelectronics Journal (MEJ), November 2003, Elsevier Publication.
5. Rabi N. Mahapatra, Editor, “Trends in Information Technology”, McGraw Hill Publications, 1998.
6. B. K. Das*, R. N. Mahapatra and B. N. Chatterji, “Modeling of Wavelet Transform on Multiprocessor Systems”, IT: Challenges and Opportunities, Tata McGraw Hill Publication, Nov.1995, pp. 335–346.
7. B. K. Das*, R. N. Mahapatra, “An Efficient Circle Detection Scheme using a Two Dimensional Array of Accumulators”, Pattern Recognition, Image Processing, and Computer Vision: Recent Advances, Narosa Publishing House, New Delhi, 1995, pp. 230-237.
8. V. A. Kumar*, B. K. Das* and R. N. Mahapatra, “Performance Analysis of Hough Transform on Parallel Architectures”, Frontiers in Parallel Computing, Narosa Publishers, 1990, pp. 279-288.