Network-on-Chip(NoC) has become default communication paradigm in System-on-Chip (SoC). The research challenges involve low power, high performance, security and scalability aspects of NoC design beyond current state of art in the industries. During the last decade, the researchers in the lab have contributed their works in the following topics.
- Interconnect Modelling
- Core-Network Interface Architecture
- Concurrent online testing
- Low Power NoC Design
- Virtual Prototypes
However, the demand for bandwidth increases exponentially with the rise in number of cores of CMPs. Traditional metallic interconnects can’t offer such an enormous bandwidth considering the power limits. On the contrary, photonic interconnects provides extremely high data rate with least power consumption. Photonic Network-on-Chip(PNoC) is the next generation on-chip communication paradigm for CMPs, which uses photonic interconnects as its building blocks. The group currently investigates the following topics
- Adaptive multiplexing in PNoC
- Multi-layer PNoC design
- Thermal management in PNoC
- Reliability aware power management in photonic data centers
- D Dang, B Patra, Rabi Mahapatra, Martin Fiers; “Mode-Division-Multiplexed Photonic Router for High-Performance Network-on-Chip”-In the proceedings of IEEE conf. on VLSI Design (VLSID)’2015, Bangalore.
- D Dang, B Patra, Rabi Mahapatra; “2-layer Laser Multiplexed Photonic Network-on-Chip” –In the proceedings of IEEE International Symposium on Quality Electronic Design(ISQED)’2015, Santa Clara, CA, USA.
- D Dang, B Patra, Rabi Mahapatra, “A Multilayered Design Approach for Efficient Hybrid 3D Photonics Network-on-chip” at ACM/SIGDA Great Lake Symposium on VLSI(GLSVLSI)’2015, Pittsburgh.
- Ayan Mandal*, Sunil P Khatri and Rabi N Mahapatra, “Exploring topologies for source-synchronous ring-based network-on-chip,” Proceedings of DATE, 2013, pp.1026-1031. (Acceptance rate: 23%)
- Suman K Mandal*, Rabi N. Mahapatra: PowerAntz: Ant behavior inspired power budget distribution scheme for Network-on-Chip systems. Microelectronics Journal 41(8): 523-531 (2010)
- Bhojwani, P.S*.; Mahapatra, R.N.; “Robust Concurrent Online Testing of Network-on-Chip-Based SoCs “,IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 16, Issue 9, Sept. 2008 Page(s):1199 – 1209