Codesign Embedded Systems

Research

The CODES Group has been active in the following research areas:

  • Network-on-Chip

     

  • Data Analytic Codesign

    • Machine Learning Algorithms & Accelerators, Reservoir Computing, read more ...

     

  • Internet of Things

    • Protocols, HW and SW Security, IoT Data Analytics, read more ...

     

  • Reconfigurable Architecture

     

  • Real-time Embedded Systems

    • Real-time Distributed embedded systems, Fair Scheduling for Multiprocessors, Reliability-aware power Management, Temperature-aware Energy Management, read more ...

 

Data Analytic Codesign

Big data analysis is an emerging research area applied to diverse sectors and is ever growing. This calls for  smart system architectures to handle data acquisition, transmission, storage, and large scale data processing. Appropriate data analytic platform (using hardware and software), is required to understand various data dynamics and discover new results hidden there. We are looking into

  • Software defined data analytic architectures.
  • Recommender Systems.
  • Predictive and Prescriptive Models and Architectures.
  • Hardware Accelerator for data partitioning and preprocessing.

Sample Publications

  • J Dass*, V. Sarin and R. Mahapatra, “Fast and Communication-efficient Algorithm for Distributed Support Vector Machine Training”, IEEE Trans. Parallel & Distributed Systems., Vol.30, Issue 5, pp. 1065-1076 May 2019. 
  • D Dang, SA Hasnain, R Mahapatra, “MReC: A Multilayer Photonic Reservoir Computing Architecture,” 20th International Symposium on Quality Electronic Design (ISQED), pp.170-175, 2019.
  • J Dass*, V. N. S. P. Sakuru , V. Sarin, R. N. Mahapatra,“Distributed QR decomposition framework for training Support Vector Machines” 37th IEEE International Conference on Distributed Computing Systems (ICDCS’17), Atlanta, GA, USA on June 5 – 8, 2017 (16.9% acceptance rate).
  • K. Lee, R. Bhattacharya, P. Sakuru*, J. Dass* and R. Mahapatra, “A Relaxed Synchronization Approach for Solving Parallel Quadratic Programming Problems with Guaranteed Convergence”, Proceedings of  30th IEEE International Parallel & Distributed Processing Symposium, pp.182-191, Chicago, 2016. (Acceptance Rate 23%)
  • A. Tripathy, A. Patra, S. Mohan and R. Mahapatra, “Distributed Collaborative Filtering on a Single Chip Cloud Computer”, in Proc. IEEE Intl. Conf. on Cloud Engineering (IC2E ’13), Mar. 25, 2013, San Francisco, CA, USA. (Acceptance Rate: 28%)
  •  Aalap Tripathy*, Ka Chon Ieong*, Atish Patra*, Rabi N. Mahapatra: “A reconfigurable computing architecture for semantic information filtering. BigData Conference 2013: 212-218 ( Acceptance rate 20%)
  • Aalap Tripathy, Suneil Mohan, Rabi Mahapatra, “Optimizing a Collaborative Filtering Recommender for Many-Core Processors”, in 6th IEEE International Conference on Semantic Computing (ICSC), September 19-21, 2012, Palermo, Italy, (Acceptance Rate: 25%)

Internet of Things

The Internet of Things (IoT) is a promise to interact with various physical systems around us in a way that is similar to web enabled  digital information happened in 2010. It has significant impact to almost all the industries. Thus, a number of challenges are to be resolved by the research community.

Our lab investigates IoT related research on the following topics:

  • IoT Security & Privacy
  • IoT Data Analytics
  • IoT Applications

There is a new course on Internet of Things Technology is being offered at multiple universities.

  • Amar A Rasheed, Rabi N Mahapatra, F G Hamza-Lup, “Adaptive group-based zero knowledge proof-authentication protocol in vehicular ad hoc networks”,IEEE Transactions on Intelligent Transportation Systems, pp.1-15, March 2019.
  • Karl Ott and Rabi Mahapatra, “Continuous Authentication of Embedded Software”, 2019 18th IEEE International Conference On Trust, Security And Privacy In Computing And Communications, PP.128-135, TrustCom 2019.
  • Karl Ott* and Rabi Mahapatra, “Hardware Performance Counters for Embedded Software Anomaly Detection, accepted for publication in Proceedings of 16th IEEE Intl. Conf. on Dependable, Autonomic and Secure Computing (DASC’2018).
  • G Bhutra, A Rasheed, R Mahapatra, “Privacy-Preserving ECG based Active Authentication (PPEA2) for IoT Devices,” IEEE 37th International Performance Computing and Communications Conference (IPCCC), pp.1-7, 2018.
  • Akash Sahoo* and Rabi Mahapatra, ” A Motif based IoT Framework for Data Efficiency”, Accepted in the Workshop on Internet of Things, Atlanta 2017.

 

Network-on-Chip

Network-on-Chip(NoC) has become default communication paradigm in System-on-Chip (SoC). The research challenges involve low power, high performance, security and scalability aspects of NoC design beyond current state of art in the industries. During the last decade, the researchers in the lab have contributed their works in the following topics.

  • Interconnect Modelling
  • Core-Network Interface Architecture
  • Concurrent online testing
  • Low Power NoC Design
  • Virtual Prototypes

However, the demand for bandwidth increases exponentially with the rise in number of cores of CMPs. Traditional metallic interconnects can’t offer such an enormous bandwidth considering the power limits. On the contrary, photonic interconnects provides extremely high data rate with least power consumption. Photonic Network-on-Chip(PNoC) is the next generation on-chip communication paradigm for CMPs, which uses photonic interconnects as its building blocks. The group currently investigates the following topics

  • Adaptive multiplexing in PNoC
  • Multi-layer PNoC design
  • Thermal management in PNoC
  • Reliability aware power management in photonic data centers

Sample Publications

  • D Dang, B Patra, Rabi Mahapatra, Martin Fiers; “Mode-Division-Multiplexed Photonic Router for High-Performance Network-on-Chip”-In the proceedings of IEEE conf. on VLSI Design (VLSID)’2015, Bangalore.
  • D Dang, B Patra, Rabi Mahapatra; “2-layer Laser Multiplexed Photonic Network-on-Chip” –In the proceedings of IEEE International Symposium on Quality Electronic Design(ISQED)’2015, Santa Clara, CA, USA.
  • D Dang, B Patra, Rabi Mahapatra, “A Multilayered Design Approach for Efficient Hybrid 3D Photonics Network-on-chip”  at ACM/SIGDA Great Lake Symposium on VLSI(GLSVLSI)’2015, Pittsburgh.
  • Ayan Mandal*, Sunil P Khatri and Rabi N Mahapatra, “Exploring topologies for source-synchronous ring-based network-on-chip,” Proceedings of DATE, 2013, pp.1026-1031. (Acceptance rate: 23%)
  • Suman K Mandal*, Rabi N. Mahapatra: PowerAntz: Ant behavior inspired power budget distribution scheme for Network-on-Chip systems. Microelectronics Journal 41(8): 523-531 (2010)
  •  Bhojwani, P.S*.; Mahapatra, R.N.; “Robust Concurrent Online Testing of Network-on-Chip-Based SoCs “,IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 16,  Issue 9,  Sept. 2008 Page(s):1199 – 1209

Real-Time Embedded Systems

The lab investigates the following topics under real-time embedded systems.

  • Real-time Distributed embedded systems
  • Fair Scheduling for Multiprocessors.
  • Reliability-aware power Management
  • Temperature-aware Energy Management

In related area, we also have looked into fast routing table lookup, high-speed packet classification, and secured wireless sensor networks

  • N. Gupta,  S. K. Mandal, A. Mandal, J. Malave & R. N. Mahapatra, “A Hardware Scheduler for Real-Time Multiprocessor System on Chip”, 23rd International Conference on VLSI Design, 2010, pp.264-269.
  • R. Sridharan and R. Mahapatra, “Reliability Aware Power Management for Dual-Processor Real-Time Embedded Systems,” Proceedings of IEEE/ACM Design Automation Conference (DAC), pp. 819-824, 2010. (Acceptance rate 25%)
  • D. Dechev, R. Mahapatra and B. Stroustrup, “Practical and Verifiable C++ Dynamic cast in Autonomous Space Systems”, Special Issue on Real-time Distributed Computing and Ubiquitous computing in Memory – Intl. Journal of Computing Science and Engineering (JCSE), December 2008.
  • R. Sridharan; N. Gupta; R. Mahapatra, “Feedback-controlled reliability-aware power management for real-time embedded systems,” Proceedings of 45th ACM/IEEE Design Automation Conference, DAC, pp. 185-190, 8-13 June 2008.
  • S. Acharya and R. Mahapatra, “A Dynamic Slack Management Technique for Real-Time Distributed Embedded System,” IEEE Transactions on Computer, Volume 57, Issue 2, pp. 215-230, Dec 2008.
  •  R. Mahapatra and W. Zhao., “An Energy efficient Slack Distribution Technique for Multimode Distributed Real-time embedded Systems”, IEEE Transactions on Parallel and Distributed Systems Volume 16, Issue 7, July 2005 pp.650 – 662.

Reconfigurable Architecture

In reconfigurable architecture, the lab contributes to “Coarse Grain Reconfigurable Architecture” (CGRA) topic. Most CGRAs composed of reconfigurable ALU arrays and configuration cache to achieve high performance and flexibility. We look into low-power design, cache management and smart control techniques to achieve high performance.

We also apply FPGA implementation to data analytic and communication problems.

  • J Dass*, Y Narawane*, R Mahapatra, V Sarin, “FPGA-based Distributed Edge Training of SVM”, Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2019)
  • Yoonjin Kim, and Rabi N. Mahapatra, “Reusable Context Pipelining for Low Power Coarse-Grained Reconfigurable Architecture,” in Proc. IEEE/ACM International Parallel & Distributed Processing Symposium (IPDPS), pp. 1-8, April 2008 (Acceptance rate 26%).
  • Yoonjin Kim, Rabi N. Mahapatra, Ilhyun Park, and Kiyoung Choi, “Low Power Reconfiguration Technique for Coarse-Grained Reconfigurable Architecture,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 17, no. 5, pp.593-603, May 2009.
  • Yoonjin Kim and Rabi N. Mahapatra, “Hierarchical Reconfigurable Computing Arrays For Efficient CGRA-based Embedded Systems,”  in the preceding of 46th IEEE/ACM Design Automation Conference, San Francisco, California, July 2009 (Acceptance rate 22%).
  • Yoonjin Kim and Rabi N. Mahapatra, “Dynamic Context Management for Low Power Coarse-Grained Reconfigurable Architecture”, in proc. the 19th IEEE/ACM Great Lake Symposium on VLSI (GLSVLSI 2009), pp. 33-38, May 2009 (Acceptance rate 16%).